1. Technical Field
The present invention relates generally to address mapping for accessing system memory, and more particularly to address mapping for memories consisting of a plurality of memory banks in which interleaving of stored information is effected.
2. Prior Art
In data processing systems, data or programs which are required for immediate processing are loaded into memory. If the loading of information blocks into memory is effected in the same consecutive sequence as they are provided, e.g. data in rows and columns of a table, or program statements in consecutive lines of a program writeup, there may be timing problems if they have to be accessed sequentially.
Thus, if blocks of data (or program segments) with consecutive block addresses are mapped on consecutive lines within one memory module, then a problem occurs if they have to be accessed in the same sequence, because usually, when access has been made to one line, the memory module needs a short period of time before the next access can be made. Accesses to consecutive block addresses therefore would need more time than is desirable.
One solution to this problem is the interleaving of data (information) in separate memory banks which can be separately accessed. Thus, if storage locations with consecutive block addresses are distributed over separate memory banks, the blocks can be accessed one immediately after the other without any waiting time. The simplest way to do this is to use the least significant portion of the given block address as the memory bank number and the remainder of the block address as internal bank address (or line-number).
However, this known method requires a number of memory banks which is a power of two, and the interleaving is uniform (sequential) which is not optimal in various applications. In general, it can be said that often, sequential accesses to memory are not randomly distributed but follow a certain pattern depending on the respective application. This is in particular true for scientific applications. Thus, even if information is stored in an interleaved manner, sequential accesses for consecutive block addresses may occur to the same memory bank. If possible, memory accesses should be distributed uniformly over all memory banks to achieve best performance.
A solution to this problem was disclosed in pending U.S. patent application Ser. No. 09/194,275, entitled xe2x80x9cAddress Mapping for System Memory.xe2x80x9d In the described method and means, given block addresses are mapped to multi-bank memory addresses by taking portions of the given address for accessing a lookup table to obtain a memory bank number stored there, and then taking a remainder of the given address as the bank internal or line address. This allowed to use arbitrary numbers of memory banks, and to achieve various different interleave factors as required by providing respective lookup tables. However, as only a single lookup operation is made for just obtaining the memory bank number, this method has some limitations and is not yet adequate for great differences in memory structure or design.
Thus, known methods and systems, though allowing some variation in the interleaving, do not have the possibility to freely select an interleaving scheme that is optimal for greatly varying types and constructions of memories.
It is, therefore, an aim of the invention to devise a method of and means for address mapping for a multibank system memory that allows a wider variety of interleaving schemes for a large range of different memory designs and that is applicable even if different memory technologies are combined in the same memory, e.g. when providing 8 M, 16 M and 64 M byte memory modules in one system.
These objects are achieved by an address mapping method for system memory and by mapping means as defined in the claims of this patent application.
The following advantages are particularly achieved by the invention:
By using lookup operations also for deriving the internal bank address (besides looking up the bank number in a table), the mapping scheme can be used for an even greater variety of memory designs combined in a single system, and an improved distribution of memory accesses for a wider variety of strides is possible. This results in a better performance for such cases which are more often encountered today.
When differently sized memory banks need to be supported, conventional methods usually apply a mix of subtract and compare operations during addressing. Such operations can be saved when the invention is used. Time will be saved due to faster memory mapping operations. In two of the implementations of the invention, the address mapping is still a single-step operation that can be provided in the addressing path. In another implementation using sequential table accesses, the application of the invention results in a significant reduction in the storage space required for the lookup tables. The invention can also be used for applications where non-contiguous address spaces are employed (xe2x80x9cholexe2x80x9d in the address space).
Other advantage s which were already achieved by the above mentioned known solution are still available with the new improved address mapping method of the present invention:
Selective interleaving schemes are possible for any number of memory banks (even non-power-of-two) and for memory banks of different sizes in the same memory. Non-integer interleave factors between one and the number of memory banks are possible. Different interleaving schemes can be effected in the same memory. Interleaving for two different power-of-two strides is possible in the same memory. Due to table-lookup, no complicated arithmetic or other processing operations are required for address mapping. The mapping scheme can easily be changed by loading different contents into the tables, or by selectively using several preloaded tables.